CAN FD Transceiver Selection Guide: Loop Delay, Bus Faults, and Low-Power Architecture

Upgrading a Controller Area Network from classic CAN 2.0 to CAN FD compresses the data-phase bit budget from$1000\text{ns}$($1\text{Mbps}$) down to$500\text{ns}$($2\text{Mbps}$) or$200\text{ns}$($5\text{Mbps}$) [1, 5]. At these speeds, physical layer propagation delays and edge asymmetry—not raw microcontroller clock speeds—govern communication stability [1, 2].

A successful transceiver selection strategy rests on five interdependent physical layer parameters:

1. Total Loop Delay ($t_{\text{LOOP}}$): Must remain low across operating temperatures (typically$100\text{ns}-150\text{ns}$, against the ISO 11898-2 ceiling of 255 ns^[2]) [1, 2].

2. Loop Delay Symmetry ($\Delta t_{\text{Bit}}$): Dictates received bit distortion at remote nodes regardless of microcontroller delay compensation [2, 5].

3. Continuous DC Bus Fault Voltage ($V_{\text{BUS}}$): Must survive direct harness shorts to battery or DC bus lines (±42 V to ±70 V^[4]) without degradation [2, 4].

4. Unpowered Bus Impedance ($I_{\text{OFF}}$): Must remain high-impedance to prevent unpowered nodes from loading active buses through internal clamping diodes [1, 3].

5. Logic Level Interfacing ($V_{\text{IO}}$): Must match low-voltage microcontroller I/O ($1.8\text{V}$to$3.3\text{V}$) directly, eliminating external level-shifter propagation delay and jitter [2].

A critical architectural rule governs this selection: Transmitter Delay Compensation (TDC) inside the microcontroller CAN controller only protects the transmitting node's internal bit check; it cannot correct physical pulse asymmetry delivered to remote receiving nodes [2, 5].

1. Executive Decision Framework: The CAN FD Selection Model

Selecting a CAN FD transceiver requires stepping through three architectural criteria before finalizing a bill of materials (BOM):

• Step 1: System Rail & Fault Environment

• 12 V Automotive (Passenger Cars): Requires$V_{\text{BUS}}$short tolerance$\ge \pm 42\text{V}$.

• 24 V Commercial / Heavy-Duty / Equipment: Requires$V_{\text{BUS}}$short tolerance$\ge \pm 58\text{V}$.

• 48 V Mild-Hybrid / Industrial Power Stages: Requires$V_{\text{BUS}}$short tolerance$\ge \pm 70\text{V}$.

• Step 2: Low-Power & Network Sleep Architecture

• Always-on or locally switched node: Standard standby mode.

• Battery-backed sleep with remote bus wake: ISO 11898-2 Wake-up Pattern (WUP)^[7] ($I_{\text{STB}}<15-20\mu \text{A}$,$0.5-5\mu \text{s}$filtering).

• Step 3: Network Topology & Data Phase Speed

• Short backplane (< 5 m) or point-to-point: Standard ISO 11898-2:2016 (up to$5\text{Mbps}$).

• Multi-drop distributed harness (2 Mbps): Standard ISO 11898-2:2016 ($<150\text{ns}{t}_{\text{LOOP}}$).

• Complex multi-drop topology (≥ 2–5 Mbps): CAN SIC (Signal Improvement Capability / CiA 601-4 / ISO 11898-2:2024).

Engineering Decision Rules

• The Voltage Rail Check: Match continuous DC fault tolerance to the worst-case continuous short-circuit rail in the wiring bundle (e.g., dual-battery jump-starts in 24V commercial systems reach 36V to 48V; 48V mild-hybrid rails experience continuous overvoltage conditions up to 58V–70V) [2, 4].

• The Thermal De-rating Rule: Never qualify a transceiver based on typical${25}^{\circ }\text{C}$loop delay. Propagation delay and pulse asymmetry widen significantly at high junction temperatures (${125}^{\circ }\text{C}\text{to}{150}^{\circ }\text{C}$AEC-Q100 Grade 1/0) [2, 7].

• The Second-Source Rule: Pin-compatible SOIC-8 or DFN-8 transceivers must match not just$V_{\text{CC}}$and pinout, but loop delay symmetry windows ($\Delta t_{\text{Bit}}$) and unpowered leakage (I_OFF)^[1] [1, 2, 6]. Divergent symmetry between alternate sources can induce sporadic bit errors at high temperatures in production [2].

2. Physical Layer Timing Physics: Loop Delay, Asymmetry, and the Controller TDC Boundary

Total Loop Delay ($t_{\text{LOOP}}$) Anatomy

Total loop delay represents the round-trip propagation time through the transceiver physical layer:

$$t_{\text{LOOP}}=t_{\text{TXD}\to \text{BUS}}+t_{\text{BUS}\to \text{RXD}}$$

• $t_{\text{TXD}\to \text{BUS}}$: The delay from the microcontroller pulling TXD low to the driver producing a differential dominant voltage ($V_{\text{DIFF}}\ge 1.5\text{V}$) across CANH and CANL [1, 2].

• $t_{\text{BUS}\to \text{RXD}}$: The delay from the differential bus crossing the receiver threshold ($V_{\text{DIFF}}\ge 0.9\text{V}$) to the transceiver pulling RXD low [1, 2].

Under ISO 11898-2:2016, the standardized maximum ceiling for$t_{\text{LOOP}}$is$255\text{ns}$when loaded by$R_L=60\Omega$,$C_L=100\text{pF}$, and$C_{\text{RXD}}=15\text{pF}$[2]. While this upper ceiling sufficed for classic 1 Mbps CAN (where a bit interval is$1000\text{ns}$), it consumes excessive timing margin at higher speeds [1, 5]. Modern high-speed CAN FD transceivers typically restrict$t_{\text{LOOP}}$to between$100\text{ns}$and$150\text{ns}$across temperature [1, 2].

The Physics of Loop Delay Asymmetry ($\Delta t_{\text{Bit}}$)

During arbitration, transceivers operate at$250\text{kbps}$or$500\text{kbps}$, where transition asymmetries represent a negligible percentage of the bit budget [1, 5]. In the CAN FD data phase, this margin collapses [1, 5].

The asymmetry stems from fundamental circuit physics:

• Dominant Transition: Actively driven by low-impedance push-pull internal MOSFETs driving CANH high and CANL low [1, 2].

• Recessive Transition: Completely passive. The driver transistors turn off, and the bus capacitance ($C_{\text{BUS}}$) discharges through the external$60\Omega$differential termination resistance ($R_{\text{TERM}}$) [1, 2].

Because active turn-on and passive turn-off rates differ, the propagation delay from recessive-to-dominant ($t_{d(\text{TXD}-\text{BUSdom})}$) rarely matches dominant-to-recessive ($t_{d(\text{TXD}-\text{BUSrec})}$) [2]. This imbalance shortens or widens the received recessive bit ($t_{\text{Bit(RXD)}}$) [2, 6].

To maintain sampling integrity, ISO 11898-2:2016 (Clauses 5.6, Tables 13 and 14) establishes standardized received recessive bit width tolerances for standard bus test loads ($60\Omega \parallel 100\text{pF}$):

If passive bus discharge or transceiver silicon asymmetry widens dominant bits, the received recessive bit ($t_{\text{Bit(RXD)}}$) shrinks below$120\text{ns}$at$5\text{Mbps}$[2]. When this occurs, remote receiving nodes whose sample points are configured near 70%–80% of the nominal bit time will sample dominant voltage during a recessive bit window, triggering a bit or stuff error [2, 5].

The Controller vs. Transceiver Boundary: Demystifying TDC

Microcontroller datasheets frequently emphasize hardware Transmitter Delay Compensation (TDC), leading some hardware designers to conclude that transceiver loop delay and symmetry are no longer critical constraints [5]. This represents an architectural misunderstanding.

What Controller TDC Does

During the fast data phase, bit duration ($200\text{ns}$at$5\text{Mbps}$) is frequently shorter than the total round-trip physical delay ($t_{\text{LOOP}}+\text{board routing}+\text{propagation}\approx 150\text{ns}-250\text{ns}$) [2, 5].

Under classic CAN rules, a transmitter samples its own RXD line at its standard sample point inside the transmitted bit to verify bus state [5]. If round-trip delay exceeds:

$$\text{Delay}>1+\text{DTSEG1}$$

(where$\text{DTSEG1}$is Data Phase Time Segment 1), the transmitted bit has not returned to RXD by the sample point [5]. Without compensation, the transmitter detects a mismatch between TXD and RXD and generates a false bit error [5].

To resolve this, the CAN FD controller TDC engine measures physical loop delay using a hardware delay counter on the TXD-to-RXD edge transition [5]. It dynamically configures a Secondary Sample Point (SSP) offset by the measured delay plus a configurable register offset ($t_{\text{TDC\_OFFSET}}$) as defined in the CAN FD Controller Module reference architecture^[5] [5]. This allows the controller to self-check bits transmitted two or more clock periods earlier without raising false bit errors [5].

What Controller TDC Cannot Do

TDC operates strictly within the transmitting microcontroller's internal digital logic [5]. It does not modify the analog differential edges driven onto the copper wiring harness [2, 5].

If a transceiver exhibits poor loop delay symmetry ($\Delta t_{\text{Bit}}$), recessive bits contract across the physical harness [2, 6]. Remote receiving nodes on the network do not use TDC for frame reception; they sample incoming data at a fixed nominal or data-phase sample point synchronized to frame transitions [5]. If the received bit width shrinks beyond the timing margin, remote nodes will mis-sample the bit, emit an active error frame, and corrupt communication [2, 5].

Selecting a transceiver with verified ISO 11898-2:2016 symmetry timing is mandatory to ensure interoperability across remote receivers, regardless of controller TDC capabilities [2, 6].

3. Electrical Survivability & Low-Power States: Bus Faults, Ground Offsets, and WUP

DC Bus Fault Survivability vs. Operational Common-Mode Range

Designers frequently confuse absolute maximum DC bus fault ratings with operational common-mode voltage range [2, 4]:

• DC Bus Fault Voltage ($V_{\text{BUS}}$Absolute Maximum): The maximum continuous direct-current voltage that can be applied to CANH or CANL with respect to local ground without causing dielectric breakdown, latch-up, or permanent hardware failure [1, 2].

• Operational Common-Mode Range ($V_{\text{CMR}}$): The electrical boundary (defined by ISO 11898-2 as$-12\text{V to}+12\text{V}$, extended in advanced automotive transceivers to$\pm 30\text{V}$) within which the differential receiver can reject common-mode offset and accurately decode valid differential data ($V_{\text{DIFF}}$) [1, 2].

Engineering Warning: A transceiver rated for$\pm 70\text{V}$bus fault protection will survive a continuous short to a$48\text{V}$battery line without hardware damage, but it cannot decode frames while the bus line remains shorted to$48\text{V}$, because that common-mode voltage exceeds the receiver's operational decoding window [2].

Low-Power Standby and Wake-up Pattern (WUP) Filtering

Battery-backed Electronic Control Units (ECUs)—such as body control modules, telematics gateways, and anti-theft systems—must remain in sub-$20\mu \text{A}$sleep states when the vehicle is parked [7].

In basic transceivers, wake-up detection relies on an unfiltered dominant bus level [7]. In automotive environments, high-energy electromagnetic pulses, inductive motor de-energization, and ground bounce easily pull differential lines into a dominant state momentarily, causing false ECU wake-ups and parasitic battery drain [7].

To prevent false wakes, ISO 11898-2:2016 defines a standardized 3-event Wake-up Pattern (WUP):

1. First Dominant Phase: Differential voltage must remain dominant continuously for at least$t_{\text{WK\_FILTER}}$($0.5\mu \text{s}\le t_{\text{WK\_FILTER}}\le 5.0\mu \text{s}$) [7].

2. Intermediate Recessive Phase: Differential voltage must transition to recessive and remain for at least$t_{\text{WK\_FILTER}}$[7].

3. Second Dominant Phase: Differential voltage must transition back to dominant for at least$t_{\text{WK\_FILTER}}$[7].

All three events must occur within the wake-up timeout window ($t_{\text{to(wake)bus}}$, typically$0.8\text{ms}-10\text{ms}$) [7]. If bus noise produces a transient$2\mu \text{s}$dominant pulse without the subsequent filtered recessive/dominant sequence, the transceiver logic rejects it, keeping the host microcontroller in sleep mode and holding standby currents below$15\mu \text{A}$[7].

The Unpowered Node Parasitic Path ($I_{\text{OFF}}$)

In partial-networking architectures, certain ECUs are depowered ($V_{\text{CC}}=0\text{V}$) to conserve energy while other nodes continue active communication across the shared bus [1, 6].

• The Failure Mode: Standard integrated circuits feature electrostatic discharge (ESD) protection structures connected between internal pins and supply rails [1]. When$V_{\text{CC}}=0\text{V}$, these diodes become forward-biased when an active transceiver drives CANH to$3.5\text{V}$[1, 2].

• The Consequences:

1. Active bus signals are clamped down to the diode forward voltage (~$0.7\text{V}$), corrupting differential signaling across the network [1, 2].

2. The unpowered node pulls current from the bus, parasitically back-powering its own$V_{\text{CC}}$rail and associated microcontroller peripherals [1].

• The Solution: Transceivers must specify low unpowered pin leakage (I_OFF ≤ ±1 μA^[6] or$\pm 3\mu \text{A}$) across$-12\text{V}\le V_{\text{BUS}}\le +12\text{V}$[1, 3]. Internal isolation circuits ensure input stages present a high-impedance state to CANH and CANL when$V_{\text{CC}}=0\text{V}$, preventing bus loading [1, 6].

4. Topology Realities vs. Vendor Myths: Harness Physics, Logic Rails, and High-Speed Limits

Dispelling the "5 Mbps Across the Harness" Fallacy

Transceiver marketing collateral often features claims of "5 Mbps" or "8 Mbps" operation [1, 3]. Hardware engineers must not assume these data rates function over long, branched vehicle harnesses [1, 8].

The physical constraints governing maximum bitrate are determined by transmission line physics:

• Harness Propagation Delay: Signals travel down automotive twisted-pair copper cable at approximately

  $5\text{ns/meter}$

  (

  $0.2\text{m/ns}$

  ) [8]. On a

  $30\text{m}$

  harness, the two-way round-trip cable delay alone is:

  $$t_{\text{prop(cable)}}=2\times 30\text{m}\times 5\text{ns/m}=300\text{ns}$$

  At

  $5\text{Mbps}$

  , the total nominal bit time is only

  $200\text{ns}$

  [2]. The cable propagation delay alone exceeds the entire bit time, rendering standard arbitration and round-trip feedback topologies unviable at that length [2, 8].

• Stub Reflections and Ringing: Industrial and automotive networks often use untuned drop lines (stubs) to connect distributed nodes [8]. When a transceiver transitions from dominant to recessive, the transmission line discontinuity at an un-terminated stub reflects energy back onto the main trunk [8].

To prevent reflections from corrupting data, critical un-terminated stub lengths must satisfy:

$$2\times t_{\text{prop(stub)}}\le \frac{1}{3}{t}_{\text{rise/fall}}$$

In practice, this requires keeping un-terminated stubs below$0.3\text{meters}$in high-speed systems [8].

On complex networks with multiple stubs, ringing extends well into the$200\text{ns}$bit window, crossing receiver thresholds and causing bit errors [2, 8]. As a result, standard ISO 11898-2:2016 CAN FD is realistically bounded to$2\text{Mbps}$on distributed topologies [2, 8]. Achieving$5\text{Mbps}$requires point-to-point links, backplanes under$5\text{meters}$, or transceivers equipped with Signal Improvement Capability (CAN SIC / CiA 601-4 / ISO 11898-2:2024) such as the TCAN857-Q1 CAN SIC transceiver^[3], which actively damp ringing during recessive transitions [3, 8].

Logic Level Integration: Dedicated$V_{\text{IO}}$vs. Discrete Level Shifters

Modern microcontrollers operate with digital I/O banks biased at$3.3\text{V}$or$1.8\text{V}$[1, 2]. However, CAN transceivers require a$5\text{V}$supply rail on$V_{\text{CC}}$to generate the ISO-standard dominant differential bus voltage ($V_{\text{DIFF}}=V_{\text{CANH}}-V_{\text{CANL}}\ge 1.5\text{V}$) [1, 2].

Attempting to resolve this with external discrete level shifters (e.g., dual-supply bidirectional translation buffers) introduces significant design risks:

• Discrete level shifters introduce$10\text{ns to}30\text{ns}$of additional propagation delay into both the transmit and receive paths.

• Unequal high-to-low and low-to-high translation times introduce external pulse skew, degrading the transceiver's loop delay symmetry before signals reach the physical bus [2].

• Increased component count consumes board space and adds failure points.

Transceivers with an integrated$V_{\text{IO}}$(or$V_{\text{L}}$) pin solve this by internally powering the digital input (TXD, STB) and output (RXD) buffers from the microcontroller's I/O rail ($1.8\text{V},2.5\text{V},\text{or}3.3\text{V}$) while powering the analog bus driver from$5\text{V}$$V_{\text{CC}}$[2, 6, 7]. This maintains tightly matched internal timing margins [2].

Mixed-Voltage Bus Compatibility ($3.3\text{V}$vs.$5\text{V}$$V_{\text{CC}}$Nodes)

Engineers frequently ask whether single-rail$3.3\text{V}$-powered CAN transceivers can communicate with standard$5\text{V}$-powered transceivers on the same physical wiring harness [1, 2].

The answer is yes, provided the 3.3V transceiver complies with ISO 11898-2 differential specifications [1, 2].

CAN is a differential protocol:

• Recessive State:$V_{\text{DIFF}}=V_{\text{CANH}}-V_{\text{CANL}}\approx 0\text{V}$[1, 2].

• Dominant State:$V_{\text{DIFF}}\ge 1.5\text{V}$(typically$2.0\text{V}$) [1, 2].

While a$5\text{V}$transceiver biases its recessive common-mode level to$2.5\text{V}$($V_{\text{CANH}}=3.5\text{V},V_{\text{CANL}}=1.5\text{V}$), compliant$3.3\text{V}$transceivers generate a dominant differential voltage ($V_{\text{DIFF}}\ge 1.5\text{V}$) with a lower common-mode bias (~$1.8\text{V}-2.0\text{V}$) [1, 2]. Because CAN differential receivers decode$(V_{\text{CANH}}-V_{\text{CANL}})$over an operational common-mode window of at least$\pm 12\text{V}$, both transceiver types interoperate reliably without signal corruption [1, 2].

5. Comparative Transceiver Matrix and Selection Trade-offs

The following table provides verified parametric specifications across representative automotive and industrial CAN FD transceivers:

Architectural Trade-off Analysis

• Ultra-Low Delay vs. Radiated EMI: Transceivers featuring faster loop delays ($<110\text{ns}$) utilize high slew-rate output stages [1, 2]. While this sharpens timing margins, it can increase high-frequency common-mode emissions [2]. High-speed designs typically require an external common-mode choke ($51\mu \text{H}\text{or}100\mu \text{H}$) to pass automotive CISPR 25 Class 5 conducted and radiated emissions limits.

• Extreme Fault Protection vs. Capacitive Loading: Transceivers providing$\pm 70\text{V}$fault survivability integrate larger internal high-voltage DMOS protection structures [2, 4]. These structures introduce higher parasitic pin capacitance on CANH and CANL (~$20\text{to}35\text{pF}$) than non-protected components, which slightly reduces the maximum allowable node count on distributed networks [2].

• Galvanic Isolation vs. Latency Budget: Galvanically isolated transceivers (e.g., ISO1042-Q1) incorporate high-voltage capacitive or magnetic isolation barriers [4]. These barriers introduce an extra$30\text{to}40\text{ns}$of internal propagation delay [4]. While necessary for operator safety and ground isolation in$400\text{V}/800\text{V}$EV battery management systems, this added latency requires larger phase buffer segments in MCU bit timing configurations [4, 5].

6. Board-Level Bring-Up, Oscilloscope Verification, and Lab Checklist

Oscilloscope Verification Setup for$t_{\text{LOOP}}$and Symmetry

Accurate measurement of sub-150 ns propagation delays and bit symmetry requires proper probing techniques and standardized bus loading [1, 2]:

1. Standard Load Fixture: Terminate the transceiver with a split-termination network: two$60\Omega$metal film resistors ($0.1\%$) in series with a$4.7\text{nF}$common-mode capacitor tied from their center tap to ground. Connect a lumped$100\text{pF}$low-inductance ceramic capacitor between CANH and CANL to simulate standard harness capacitance [2].

2. Probe Calibration: Use high-bandwidth active single-ended probes ($\ge 500\text{MHz}$, input capacitance$\le 2\text{pF}$) for TXD and RXD. Standard passive$10\times$probes with long ground leads introduce inductive ground ringing that will invalidate sub-200 ns timing measurements. Use a calibrated differential probe across CANH and CANL [2].

3. Loop Delay Measurement: Set the oscilloscope to trigger on the falling edge of TXD at the 50% voltage threshold ($1.65\text{V}$on a$3.3\text{V}$system). Measure the time delta ($\Delta t$) to the corresponding 50% falling edge on RXD [2]. This is$t_{\text{LOOP(recessive-to-dominant)}}$[2]. Repeat for the rising edge to determine$t_{\text{LOOP(dominant-to-recessive)}}$[2].

4. Received Bit Symmetry ($\Delta t_{\text{Bit}}$) Measurement: Transmit a bitstream containing alternating bits (10101010) and single recessive bits surrounded by dominant bits at the target data phase rate ($2\text{Mbps}$or$5\text{Mbps}$) [2]. Measure the pulse width of the recessive bit on RXD at the 50% logic threshold [2]. Verify that the measured width falls within the ISO 11898-2:2016 limits ($400\text{ns}-550\text{ns}$for 2 Mbps;$120\text{ns}-220\text{ns}$for 5 Mbps) [2].

FDCAN External Loop-back Mode

Pre-Hardware Firmware Validation: FDCAN Loopback Modes

Microcontroller peripherals (e.g., STM32 FDCAN, TI MCAN) provide internal and external loopback modes to validate protocol software prior to PCB assembly:

• Internal Loopback Mode: The CAN core disconnects its receive engine from the physical FDCAN_RX pin and forces the physical FDCAN_TX pin to hold a continuous recessive state ($=1$). Transmitted bits route directly from the transmit shift register to the receive shift register internally. This mode enables developers to verify Message RAM allocation, FIFO handling, and Bitrate Switching (BRS) firmware without placing signal transitions onto an active harness.

• External Loopback Mode: The peripheral routes its transmit engine back to its receive engine internally, but also continues driving the physical FDCAN_TX pin. This enables developers to probe the physical output pins and verify baud-rate prescalers and bit timing segment configurations using an oscilloscope, even before mounting external transceivers.

Practical Loopback Verification Traps

• The "Scope Trap" on RXD: During external loopback mode, the feedback from TX to RX occurs entirely within the microcontroller silicon. The physical FDCAN_RX GPIO pin is disconnected from the receive engine. Probing the RXD pin will show a flatline, even while the firmware receives valid frames into its receive FIFO. Only the physical TXD pin transitions.

• The ACK Masking Pitfall: In loopback modes, the CAN controller automatically acknowledges its own transmitted frames within the peripheral macro. The frame will succeed even if no partner node is attached and no termination resistors are present. Loopback modes do not validate bus loading, harness impedance, split termination, or partner transceiver ACK generation.

Hardware Bring-Up & Schematic Review Checklist

• [ ] Bus Termination: Verified$120\Omega$total bus termination (typically two$60\Omega$resistors with a central$4.7\text{nF}$capacitor to ground for common-mode filtering).

• [ ] Supply Rail Decoupling: Placed a$0.1\mu \text{F}$low-ESR ceramic capacitor directly adjacent to the$V_{\text{CC}}$pin, accompanied by a$4.7\mu \text{F}$ceramic bulk capacitor.

• [ ] Logic Level Alignment: If using a transceiver with a$V_{\text{IO}}$pin, verified that$V_{\text{IO}}$is tied directly to the microcontroller's I/O supply ($1.8\text{V}$or$3.3\text{V}$) and decoupled with a$0.1\mu \text{F}$capacitor.

• [ ] ESD and Transients: Placed bidirectional AEC-Q101 compliant ESD suppression diodes immediately adjacent to the board connector, ahead of the common-mode choke.

• [ ] Common-Mode Choke (CMC): Placed a common-mode choke ($51\mu \text{H}$or$100\mu \text{H}$) between the ESD diodes and transceiver bus pins to suppress emissions without degrading differential edge rates.

• [ ] Unpowered Bus Integrity ($I_{\text{OFF}}$): Verified that the selected transceiver specifies$I_{\text{OFF}}\le \pm 1\mu \text{A}$across$-12\text{V}\le V_{\text{BUS}}\le +12\text{V}$if the node will be unpowered on an active network [1, 3].

• [ ] DC Fault Safety Margin: Checked that the transceiver continuous DC fault withstand rating exceeds the highest voltage rail present in the harness bundle [2, 4].

7. Frequently Asked Questions (FAQ)

Does the Microchip MCP2515 stand-alone controller support CAN FD?

No. The MCP2515 is a legacy SPI controller that supports classic CAN 2.0B up to 1 Mbps only. It cannot parse the flexible data payload (up to 64 bytes) or bit-rate switching fields of CAN FD frames. Upgrading a design requires a CAN FD controller such as the MCP2517FD or MCP2518FD, or a microcontroller with integrated CAN FD hardware.

Can a classic CAN 2.0 transceiver be used in a CAN FD network operating at 2 Mbps?

No. While classic transceivers can physically transition fast enough to transmit 1 Mbps arbitration frames, they lack certified loop delay symmetry ($\Delta t_{\text{Bit}}$) specifications [2]. Their passive dominant-to-recessive transitions are not sufficiently controlled, causing recessive bits to shorten during 2 Mbps or 5 Mbps data phases [2]. Remote nodes will mis-sample these shortened bits and emit active error frames [2].

How does termination resistance tolerance affect loop delay and bit symmetry?

Because the dominant-to-recessive transition is passive, the bus discharge rate is determined by the $RC$ time constant formed by the differential termination resistance and lumped network capacitance:

$$\tau =R_{\text{TERM}}\times C_{\text{BUS}}$$

If termination resistance increases (e.g., missing termination resistors, open traces, or degraded components),$\tau$increases. The recessive discharge slows, extending the dominant-to-recessive delay and shrinking the received recessive bit width ($t_{\text{Bit(RXD)}}$) [2].

What is the functional difference between CAN FD and CAN SIC transceivers?

Standard CAN FD transceivers (ISO 11898-2:2016) drive dominant states actively and rely entirely on external termination resistors to discharge the bus to recessive [1, 2]. On networks with long stubs, the impedance mismatches cause signal reflections (ringing) during recessive transitions [8].

CAN SIC transceivers (complying with CiA 601-4 and ISO 11898-2:2024) incorporate active circuitry that engages during recessive transitions to actively damp ringing on the bus [3, 8]. This suppresses reflections, preserves recessive bit widths, and allows data rates of 2 Mbps to 5 Mbps to operate reliably over complex, branched wiring harnesses without requiring point-to-point topologies [3, 8].

Sources and references used for this guide

1. TCAN332G 3.3-V CAN Transceivers with CAN FD Part Details
   Source type: official company documentation
   Used for: Loop delay specifications (<135 ns), 3.3V VCC operation, unpowered high-impedance pin behavior (IOFF), and operating temperature ranges.
   Caution: Vendor product documentation; reflects performance under specific standard capacitive bus load conditions.

2. TCAN1042 Fault Protected CAN Transceiver with CAN FD
   Source type: official company documentation
   Used for: DC bus fault protection voltage ratings up to ±70V, propagation delay symmetry, and automotive physical layer compliance.
   Caution: Vendor datasheet; DC fault withstand voltage must not be confused with active common-mode operating range.

3. TCAN857-Q1 Automotive Fault-Protected CAN FD Transceiver Datasheet
   Source type: official company documentation
   Used for: ISO 11898-2:2024 compliance details, advanced thermal shutdown, TXD dominant timeout, and high-voltage fault protection.
   Caution: Vendor datasheet; references emerging ISO 11898-2:2024 standard which incorporates latest physical layer requirements.

4. ISO1042 Isolated CAN Transceiver With 70-V Bus Fault Protection
   Source type: official company documentation
   Used for: Galvanic isolation architectures, 152 ns loop delay characteristics, and high-voltage industrial CAN FD survivability.
   Caution: Specific to isolated transceiver architectures; isolation barriers introduce additional timing considerations compared to non-isolated transceivers.

5. MCP25XXFD Family Reference Manual - CAN FD Controller Module
   Source type: official company documentation
   Used for: Transmitter Delay Compensation (TDC) mechanics, Secondary Sample Point (SSP) calculation, and controller bit-error boundary conditions.
   Caution: Focuses on CAN controller digital IP registers and timing; must be distinguished from physical transceiver delay characteristics.

6. TJF1051 High-Speed CAN Transceiver Datasheet
   Source type: official company documentation
   Used for: ISO 11898-2:2016 loop delay symmetry definitions, received bit width tolerances, and unpowered node behavior.
   Caution: Vendor datasheet provided via authorized distributor document repository.

7. TLE9252V Dual CAN FD Transceiver Technical Overview
   Source type: official company documentation
   Used for: ISO 11898-2:2016 compliant 5 Mbps loop delay symmetry, Wake-up Pattern (WUP) filtering times (0.5 µs to 5 µs), and standby modes.
   Caution: Distributor catalog entry summarizing manufacturer technical datasheet specifications.

8. TLE9351SJ High-Speed CAN FD Transceiver Datasheet Overview
   Source type: official company documentation
   Used for: VeLIO certification, SAE J2284-4/5 compliance, and 5 Mbps automotive loop delay symmetry.
   Caution: Distributor summary; verify detailed switching waveforms directly against Infineon engineering specifications.